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AND
OR
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XNOR
NOT
BUF
TRI
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T-FF
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JK-FF
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LFSR
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JTAG
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IR
CU
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IMM
PIPE
HS
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7SEG
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PROPERTIES
Label
Value
0
Steps
Value
0
Steps
Init Q
0
Size
2
4
8
16
Bit Width
1
2
4
8
16
32
64
Seed
Taps
Golden
Run Len
Sig Bits
1
2
4
8
16
32
Golden
IR Bits
2
3
4
5
6
8
16
IDCODE
Addr Bits
1
2
3
4
5
6
8
12
16
24
Lines
Mapping
direct
set-associative
fully-associative
Ways
Write Policy
write-through
write-back
Control
+ STALL
+ FLUSH
WIRE PROPERTIES
Net Name
Color
Auto
Red
Green
Blue
Yellow
Purple
Orange
Cyan
Pink
Clock Wire
OFF
Stuck-at
none
s-a-0
s-a-1
Open
OFF
Bridge w/
none
Bridge mode
wired-OR
wired-AND
RESET ROUTE
CLEAR ALL
BREAKPOINTS
+ ADD ON SELECTED
CLEAR ALL
WAVEFORM
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β¨ SIGNALS
+
BMK
TRIG
DEC
FIT
βΆ FULL
.VCD
IMPORT
.PNG
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DEBUG
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WATCH LIST
+ WATCH SELECTED
CLEAR
DIAGNOSTICS
enabled
SIGNAL TRACE
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← TRACE BACKWARD
STOP TRACE
TRUTH TABLE
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ANALYSIS
STAGES
RETIME
FULLSCREEN
EXPORT
JSON snapshot
CSV metrics
Markdown report
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DFT
GEN RANDOM
RUN FAULT SIM
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KEYBOARD SHORTCUTS
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CONTROL UNIT β OPCODE TABLE
BRANCH PREDICTOR
Static Not-Taken
Static BTFN
1-bit (last-outcome)
2-bit saturating
Opcodes:
4
8
16
32
64
128
256
RESET DEFAULT
SAVE
CLOSE
OP
NAME
ALU_OP
REG_WE
MEM_WE
MEM_RE
JMP
HALT
IMM
HEX
ROM EDITOR
C
ASM
TABLE
LOAD FILE
SAVE
CLOSE
ADDR
HEX
ASSEMBLY
INSERT
RETIME SUGGESTION
Reject
Accept
Pipeline balanced.
Press Ctrl+Z to undo
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.v
file here
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Multi-file: drop a folder or pick many files. The top-module dropdown lists every module across them.
Top module:
Top:
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Mode:
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FIDELITY (preserve source verbatim)
REPLACE CURRENT
ADD AS SUB-CIRCUIT
VERILOG PREVIEW β
circuit.v
top:
header
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TESTBENCH
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Generating Verilogβ¦
0
lines
0
ports
0
nets
0
assigns
0
always
0
mem
0
TODOs
Verify with
iverilog -g2005 -o sim circuit.v && vvp sim
. Tested clean against Icarus Verilog.
EXAMPLES
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